ctrl_logic + axis架构设计思路

一、ap_memory + axilite + axi_stream架构

二、代码框架

void param_array_top
(
hls::stream<ap_uint<32> >& src,
hls::stream<ap_uint<32> >& dst,
ap_uint<32> param_cfg[128]//axilite_ap_memory,generate bram logic
){
#pragma HLS RESOURCE variable=param_cfg core=RAM_2P_BRAM
#pragma HLS INTERFACE axis register both port=src
#pragma HLS INTERFACE axis register both port=dst
#pragma HLS INTERFACE s_axilite port=return bundle=CONTROL_BUS
#pragma HLS INTERFACE s_axilite port=param_cfg bundle=CONTROL_BUS

staitc ap_uint<32> local_param_1;
staitc ap_uint<32> local_param_2;
staitc ap_uint<32> local_param_3;
staitc ap_uint<32> local_param_4;
staitc ap_uint<32> local_param_5;

staitc ap_uint<32> local_param[128];

#pragma HLS RESOURCE variable=local_param core=RAM_2P_LUTRAM

local_param_1 = param_cfg[0];
local_param_2 = param_cfg[1];
local_param_3 = param_cfg[2];
local_param_4 = param_cfg[3];
local_param_5 = param_cfg[4];

kernel_process(src,dst,&param_cfg[0],local_param_1);

}

void kernel_process
(
hls::stream<ap_uint<32> >& src,
hls::stream<ap_uint<32> >& dst,
ap_uint<32> param_cfg[128],
ap_uint<32> local_param_1
){

#pragma HLS DATAFLOW

read_stream();
proc_stream();
write_stream();

}