setMessageLimit 1000
set DESIGN IF_ASIC_TOPset init_lef_file " \/home/xxx.tlef \/home/xxx.lef \/home/xxx.lef \/home/xxx.lef \/home/xxx.lef \/home/xxx.lef \/home/xxx.lef \" #/home/xxx.lef \
#/home/xxx.tlef \
#/home/xxx.lef \set init_top_cell ${DESIGN}
set init_gnd_net GND
set init_pwr_net {VCC3V3 VCC1V8}
##set NETLIST_VER VHDL0113_1353/
if {[info exists env(NETLIST_VER)]} { set NETLIST_VER $env(NETLIST_VER) }
set init_verilog " /home/xxx.map.v \ /home/xxx.v \ "set SDC_FILE "/home/xxx.sdc"set init_mmmc_file "/home/xxx.tcl"init_designset_timing_derate -late -cell_delay 1.1
set_timing_derate -early -cell_delay 0.9
