从HDMI规范看HDMI接口电路设计
HDMI规范概述
• TMDS
Transition Minimized Different Signal
3路数据通道、1路时钟通道
• TMDS Character
A 10bit TMDS-encode value
1个TMDS Clock周期传输1个Character
• Tbit
Time duration of a single bit carried across the TMDS data channels
• Tcharacter
Time duration of a single TMDS character carried
across the TMDS data channels
Tcharacter = 10 * Tbit
• TMDS Clock = Pixel Clock(at the default 24bit)
24 bit mode: TMDS clock = 1.0 x pixel clock
30 bit mode: TMDS clock = 1.25 x pixel clock
36 bit mode: TMDS clock = 1.5 x pixel clock
48 bit mode: TMDS clock = 2.0 x pixel clock
25Mhz-340Mhz
若视频格式需要的TMDS Clock小于25Mhz，例如480i，使用策略：pixel-repetition scheme
• DDC Display Data Channel
用于Source和Sink交换配置/状态信息
max rate 100Khz
• HPD Hot Plug Detect
用于热插拔检测/+5V Power Signal检测
at least 100ms
• Pixel Size
24 bit(default)、30bit、36bit、48bit
Encoded in RGB、YCbCr 444 or YCbCr 422
• Video
8b --> 10b
Transition Minimized Encoding
• Audio and Auxiliary Data
4b -->10b
类似Transition Minimized Encoding
TMDS Error Reduction Encoding-4bit
• Control Data
2b --> 10b
Hsync/Vsync/CTL[0:3]
Transition Maximized Encoding
**HDMI电路设计需要参考的标准
• Current Source
电流源驱动
常用接口芯片8mA~16mA
• AVcc
+3.3V(±5%)
DC耦合
• Rt termination resistance
50 ohms (±10%)
与Z0匹配
差分100ohms
• Vswing
High level voltage = AVcc
Low level voltage = Avcc - Vswing
**
以TP1为例
• DC Characteristic
Single–ended standby output voltage AVcc±10mV
Single–ended output swing voltage 400mV ≤ Vswing ≤ 600mV
Single–ended high level output voltage
if attached Sink supports only <=165MHz :
AVcc±10mV
if attached Sink supports >165MHz :
( AVcc – 200mV) ≤ VH ≤ (AVcc + 10mV)
Single-ended low level output voltage
if attached Sink supports only <=165MHz :
(AVcc – 600mV) ≤ VL ≤ (AVcc – 400mV)
if attached Sink supports >165MHz :
( AVcc – 700mV) ≤ VL ≤ (AVcc – 400mV)
• AC Characteristic
Rise time / fall time (20%-80%) 75psec ≤ Rise time / fall time
Intra-Pair Skew at Source Connector Max 0.15*Tbit
Inter-Pair Skew at Source Connector Max 0.20*Tcharacter
Clock duty cycle Min40% / Average50% /Max 60%
TMDS Differential Clock Jitter, max 0.25 Tbit
• +5V Power Singal
Source提供给Sink端
TP1提供的+5V范围：Min 4.8V Max 5.3V
要求Source最少的带载能力 55mA
线缆最少的带载能力 50mA
• An HDMI Source shall have +5V Power signal over-current protection of no more than 0.5A
• Sink
High voltage level Min 2.4V Max 5.3V
Low voltage level Min 0V Max 0.4V
Output resistane 1K ohms±20%
• Source
High voltage level Min 2.0V Max 5.3V
Low voltage level Min 0V Max 0.8V
HPD由Sink驱动，为防止误判Source端必须要下拉,下拉电阻阻值要足够大。常用47K~100K
重新配置需要拉低至少100ms
• DDC/I2C
使用I2C协议/ I2C Standard Mode/Max 100Khz
Source端SCL/SDA上拉电阻 Min 1.5Kohms/Max 2Kohms
Sink端SCL上拉电阻 47Kohms
电压 4.5V-5.5V
• Maximum Capacitance of DDC line
HDMI Source 50pF
Cable Assembly 700pF
HDMI Sink 50pF