verilog HDLBits刷题[Finite State Machines]“Fsm1”---Simple FSM1(asynchronous reset)

1、题目

This is a Moore state machine with two states, one input, and one output. Implement this state machine. Notice that the reset state is B.

This exercise is the same as fsm1s, but using asynchronous reset.

2、分析

Moore 有限状态机：输出只由当前状态决定

3、代码

module top_module( input clk, input areset, // Asynchronous reset to state B input in, output out);// parameter A=1'b0, B=1'b1; reg state, next_state; always @(*) begin // This is a combinational always block case(state) A:next_state=in?A:B; B:next_state=in?B:A; endcase end always @(posedge clk, posedge areset) begin // This is a sequential always block if(areset) state<=B; else state<=next_state; end assign out = (state ==B); endmodule

4、结果