verilog HDLBits刷题[Finite State Machines]“Fsm3”---Simple FSM 3 （asynchronous reset）
1、题目
See also: State transition logic for this FSM
The following is the state transition table for a Moore state machine with one input, one output, and four states. Implement this state machine. Include an asynchronous reset that resets the FSM to state A.
| State | Next state | Output | |
|---|---|---|---|
| in=0 | in=1 | ||
| A | A | B | 0 |
| B | C | B | 0 |
| C | A | D | 0 |
| D | C | B | 1 |
2、分析
使用one-hot state encoding: A=4'b0001, B=4'b0010, C=4'b0100, D=4'b1000.（还是有点困惑）
parameter A=0, B=1, C=2, D=3;
A,B,C,D=bit 下标
state[A]→state[0]state[B]→state[1]state[C]→state[2]state[D]→state[3]
独热编码规则：
- 在状态 A：
state = 4'b0001→state[0]=1 - 在状态 B：
state = 4'b0010→state[1]=1 - 在状态 C：
state = 4'b0100→state[2]=1 - 在状态 D：
state = 4'b1000→state[3]=1
3、代码
module top_module( input clk, input in, input areset, output out); // reg [3:0] state,next_state; parameter A=0, B=1, C=2, D=3; // State transition logic: Derive an equation for each state flip-flop. assign next_state[A] = state[0]&(~in) | state[2]&(~in); assign next_state[B] = state[0]&(in) | state[1]&(in)|state[3]&(in); assign next_state[C] = state[1]&(~in) | state[3]&(~in); assign next_state[D] =state[2]&(in); always @(posedge clk ,posedge areset)begin if(areset) state<=4'd1; else state<=next_state; end // Output logic: assign out = (state[D]==1'b1); endmodule4、结果