verilog HDLBits刷题[Finite State Machines]“Exams/2014 q6b”---Q6b:FSM next-state logic

1、题目

Consider the state machine shown below, which has one inputwand one outputz.

Assume that you wish to implement the FSM using three flip-flops and state codesy[3:1] =000, 001, ... , 101 for states A, B, ... , F, respectively. Show a state-assigned table for this FSM. Derive a next-state expression for the flip-flopy[2].

Implement just the next-state logic fory[2]. (This is much more a FSM question than a Verilog coding question. Oh well.)

2、分析

照图说话嘛，最后推导Y2的下一状态的表达式

3、代码

module top_module ( input [3:1] y, input w, output Y2); parameter A=3'b000,B=3'b001,C=3'b010,D=3'b011,E=3'b100,F=3'b101; reg [2:0]next_state; always@(*)begin case(y) A: next_state=w?A:B; B:next_state=w?D:C; C:next_state=w?D:E; D:next_state=w?A:F; E:next_state=w?D:E; F:next_state=w?D:C; default:next_state=A; endcase end assign Y2=next_state[1]; endmodule