verilog HDLBits刷题[Building Larger Circuits]“Exams/review2015 fsmseq”---FSM :Sequence 1101 recognizer

1、题目

This is the second component in a series of five exercises that builds a complex counter out of several smaller circuits. See the final exercise for the overall design.

Build a finite-state machine that searches for the sequence 1101 in an input bit stream. When the sequence is found, it should set start_shifting to 1, forever, until reset. Getting stuck in the final state is intended to model going to other states in a bigger FSM that is not yet implemented. We will be extending this FSM in the next few exercises.

2、分析

构建状态机：寻找序列1101，找到后将start_shifting永久置1直到复位的出现才变为0；

该序列有4bit，如果加上IDEL，一共5个状态，到第5个状态后，也就是已经找到1101后，不管输入是什么，输出一直保持1，第五个状态后就保持第五个状态

3、代码

module top_module ( input clk, input reset, // Synchronous reset input data, output start_shifting); parameter IDEL=3'd0,BIT1=3'd1,BIT2=3'd2,BIT3=3'd3,BIT4=3'd4; reg [2:0]state,next_state; always@(posedge clk)begin if(reset) state<=IDEL; else state<=next_state; end always@(*)begin case(state) IDEL:next_state=data?BIT1:IDEL; BIT1:next_state=data?BIT2:IDEL; BIT2:next_state=data?BIT2:BIT3; BIT3:next_state=data?BIT4:IDEL; BIT4:next_state=BIT4; default:next_state=IDEL; endcase end assign start_shifting=(state==BIT4); endmodule

4、结果