verilog HDLBits刷题[Building Larger Circuits]“Exams/review2015 shiftcount”---4-bit shift register...

1、题目

This is the first component in a series of five exercises that builds a complex counter out of several smaller circuits. See the final exercise for the overall design.

Build a four-bit shift register that also acts as a down counter. Data is shifted in most-significant-bit first when shift_ena is 1. The number currently in the shift register is decremented when count_ena is 1. Since the full system doesn't ever use shift_ena and count_ena together, it does not matter what your circuit does if both control inputs are 1 (This mainly means that it doesn't matter which case gets higher priority).

2、分析

做一个四位移位寄存器

• 当shift_ena = 1（移位使能有效）：数据从最高位 MSB 优先移入寄存器（我认为这句话是错的，代码的做法应该是移入最低位，左移）；

• 当count_ena = 1（计数使能有效）：寄存器内存储的 4 位数值做减 1 递减；

• 系统运行过程中永远不会同时让 shift_ena 和 count_ena 都等于 1；因此两个使能同时为 1 时，电路输出任意结果都合法，无需纠结优先级。

3、代码

module top_module ( input clk, input shift_ena, input count_ena, input data, output [3:0] q); reg [3:0]q_tmp; always@(posedge clk)begin q_tmp<=4'd0; if(shift_ena) q_tmp<={q_tmp[2:0],data}; else if(count_ena) q_tmp<=q_tmp-1'b1; else q_tmp<=q_tmp; end assign q=q_tmp; endmodule

4、结果