Xilinx FPGA实现延时链

　　之前有做一个输出100ps左右的延时链，当时找到一篇国外的论文，2015年的文章了。链接：《High-Resolution_Synthesizable_Digitally-Controlled_Delay_Lines》，根据论文的内容，要使输出的延时能够更加的准确，这里输出端保持不变，输入端走的是时钟的走线，这样做到了尽可能保证走线的时间一致，只跟原语CARRY4的单元延时有关。

　　话不多说，直接上代码，由于没有更精确的设备进行测量延时，所以代码仅供参考。

module delay_chain
#(
    parameter                BUF_TYPE        = "BUFG"          ,
    parameter                RESOLUTION      = "COARSE"        ,
    parameter                CARRY4_STAGE    = 16            
)
(
    input                    i_signal                          ,
    input    [9:0]           i_carry_num                       ,
    output                   o_signal                        
);

    wire                            w_signal_buf               ;
    wire    [4*CARRY4_STAGE-1:0]    w_stage_buf                ;


    generate
        if(BUF_TYPE == "BUFR")
        begin:BUF1
            BUFR
            #(
                .BUFR_DIVIDE           ( "BYPASS"                     ),
                .SIM_DEVICE            ( "7SERIES"                    )
            )
            BUFR_inst
            (
                .O                     ( w_signal_buf                 ),
                .CE                    ( 1'b1                         ),
                .CLR                   ( 1'b0                         ),
                .I                     ( i_signal                     )
            );
        end
        else if(BUF_TYPE == "BUFH")
        begin:BUF2
            BUFH BUFH_inst
            (
                .O                     ( w_signal_buf                  ),
                .I                     ( i_signal                      )
            );
        end
        else
        begin:BUF3
            BUFG BUFG_inst
            (
                .O                     ( w_signal_buf                  ),
                .I                     ( i_signal                      )
            );
        end
    endgenerate


    integer           i;
    genvar            n;
    
    generate
        if(RESOLUTION == "COARSE")
        begin
            reg        [CARRY4_STAGE-1:0]        r_carry_sel;
            wire       [CARRY4_STAGE-1:0]        w_carry_sel;
            
            always@(*)
            begin
                r_carry_sel = 'd0;
                for(i = 0; i <= CARRY4_STAGE - 1; i = i + 1)
                    if(i_carry_num == i)
                        r_carry_sel[CARRY4_STAGE-1-i] = 1'b1;
            end
            assign w_carry_sel = ~r_carry_sel;
            
            for(n = 0; n <= CARRY4_STAGE - 1; n = n + 1)
            begin
                if(n == 0)
                begin:carry4_first
                    CARRY4 CARRY4_inst
                    (
                        .CO            ( w_stage_buf[3:0]            ),
                        .O             (                             ),
                        .CI            ( 1'b0                        ),
                        .CYINIT        ( 1'b0                        ),
                        .DI            ( {3'b000,w_signal_buf}       ),
                        .S             ( {3'b111,w_carry_sel[0]}     )
                    );
                end
                else
                begin:carry4_X
                    CARRY4 CARRY4_inst
                    (
                        .CO            ( w_stage_buf[4*(n+1)-1:4*n]  ),
                        .O             (                             ),
                        .CI            ( w_stage_buf[4*n-1]          ),
                        .CYINIT        ( 1'b0                        ),
                        .DI            ( {3'b000,w_signal_buf}       ),
                        .S             ( {3'b111,w_carry_sel[n]}     )
                    );
                end
            end
        end
        else
        begin
            reg        [4*CARRY4_STAGE-1:0]        r_carry_sel;
            wire       [4*CARRY4_STAGE-1:0]        w_carry_sel;
            
            always@(*)
            begin
                r_carry_sel = 'd0;
                for(i = 0; i <= 4*CARRY4_STAGE - 1; i = i + 1)
                    if(i_carry_num == i)
                        r_carry_sel[4*CARRY4_STAGE-1-i] = 1'b1;
            end
            assign w_carry_sel = ~r_carry_sel;
            
            for(n = 0; n <= CARRY4_STAGE - 1; n = n + 1)
            begin
                if(n == 0)
                begin:carry4_first
                    CARRY4 CARRY4_inst
                    (
                        .CO                ( w_stage_buf[3:0]            ),
                        .O                 (                             ),
                        .CI                ( 1'b0                        ),
                        .CYINIT            ( 1'b0                        ),
                        .DI                ( {4{w_signal_buf}}           ),
                        .S                 ( w_carry_sel[3:0]            )
                    );
                end
                else
                begin:carry4_X
                    CARRY4 CARRY4_inst
                    (
                        .CO                ( w_stage_buf[4*(n+1)-1:4*n]  ),
                        .O                 (                             ),
                        .CI                ( w_stage_buf[4*n-1]          ),
                        .CYINIT            ( 1'b0                        ),
                        .DI                ( {4{w_signal_buf}}           ),
                        .S                 ( w_carry_sel[4*(n+1)-1:4*n]  )
                    );
                end
            end
        end
    endgenerate
    
    assign o_signal = w_stage_buf[4*CARRY4_STAGE - 1];
    
endmodule