AHB总线读写RAM

`timescale 1ns/1ps

module ahb2ram #(parameter ADDR_BITS = 32) (
input resetn,
input ahb_clock,
input [1:0] ahb_htrans,//传输类型00：idle, 01:busy, 10:NONSEQ, 11:SEQ NONSEQ：新数据 SEQ:连续传输 IDLE:空闲 BUSY:忙
input [2:0] ahb_hsize,
input [31:0] ahb_hwdata,
input [31:0] ahb_haddr,
input ahb_hwrite,
output reg [31:0] ahb_hrdata,
output reg ahb_hreadyout,
output [ADDR_BITS-3:0] ram_addr,
output reg [3:0] ram_byteena,
output [31:0] ram_data,
output reg ram_wren,
output ram_rden,
input [31:0] ram_q
);
// All AHB signals assume 1 cycle latency from RAM (no output register)
//写时序说明
//1. 在 T0 上升沿：
// - 主机驱动地址 HADDR
// - 设置 HTRANS = NONSEQ
// - 设置 HWRITE = 1
// - 从机在该上升沿采样地址与控制信号
//
//2. 在 T1 上升沿：
// - 主机驱动写数据 HWDATA
// - 从机在 HREADY=1 的情况下采样 HWDATA
// - 若 HREADY=0，主机必须保持所有信号不变
//
//3. 若 HREADY=0：
// - 主机在后续每个时钟周期保持
// HADDR / HTRANS / HWRITE / HWDATA
// - 直到从机拉高 HREADY
// - 在 HREADY=1 的上升沿，写数据被正式采样

reg [ADDR_BITS-1:0] haddr_reg;
reg [2:0] hsize_reg;
reg [31:0] ram_qd;
reg rd_en_d1;//打拍
reg rd_en_d2;//采样ram_q
reg rd_en_d3;//驱动HRDATA
//AHB读数据 NONSEQ / SEQ
//在AHB读操作中,RAM 具有1拍读延迟，而从机必须在 HREADY=1 的那一拍提供有效的 HRDATA；
//因此需要在读开始时拉低 ahb_hreadyout，插入一拍等待，使 RAM 读数据与 AHB 数据阶段对齐
wire rd_en = !ahb_hwrite && (ahb_htrans[1] || !ahb_hreadyout);

always @ (posedge ahb_clock or negedge resetn) begin
if (!resetn) begin
ram_byteena <= 4’b1111;
end else if (ahb_htrans[1] && ahb_hwrite) begin
if (ahb_hsize == 3’b000) begin // byte write
case(ahb_haddr[1:0])
2’b00: ram_byteena <= 4’b0001;
2’b01: ram_byteena <= 4’b0010;
2’b10: ram_byteena <= 4’b0100;
2’b11: ram_byteena <= 4’b1000;
default: ram_byteena <= 4’hX;
endcase
end else if (ahb_hsize == 3’b001) begin // halfword write
case (ahb_haddr[1])
1’b0: ram_byteena <= 4’b0011;
1’b1: ram_byteena <= 4’b1100;
default:ram_byteena <= 4’hX;
endcase
end else begin // word (including above) write
ram_byteena <= 4’b1111;
end
end
end

always @ (posedge ahb_clock or negedge resetn) begin
if (!resetn) begin
hsize_reg <= 3’b0;
end else if (ahb_htrans[1]) begin
hsize_reg <= ahb_hsize;
end
end

always @ (posedge ahb_clock or negedge resetn) begin
if (!resetn)
ram_wren <= 0;
else if (ahb_htrans[1] && ahb_hwrite)
ram_wren <= 1;
else
ram_wren <= 0;
end

always @ (posedge ahb_clock or negedge resetn) begin
if (!resetn)
haddr_reg <= 0;
else if (ahb_htrans[1] & ahb_hwrite && ahb_hreadyout)
haddr_reg <= ahb_haddr[ADDR_BITS-1:0];
else if (ahb_htrans == 2’b10 && !ahb_hwrite && ahb_hreadyout)
haddr_reg <= ahb_haddr[ADDR_BITS-1:0];
else if (ahb_htrans == 2’b11 && !ahb_hwrite && rd_en_d1)
haddr_reg <= haddr_reg + (1 << hsize_reg);
end

always @ (posedge ahb_clock or negedge resetn) begin
if (!resetn) begin
rd_en_d1 <= 0;
rd_en_d2 <= 0;
rd_en_d3 <= 0;
end else begin
rd_en_d1 <= rd_en;
rd_en_d2 <= rd_en_d1;
rd_en_d3 <= rd_en_d2;
end
end

always @ (posedge ahb_clock or negedge resetn) begin
if (!resetn)
ahb_hreadyout <= 1;
else if (rd_en && !rd_en_d1)//第一个上升沿
ahb_hreadyout <= 0;
else if (rd_en_d3 && rd_en_d2)//
ahb_hreadyout <= 1;
end

always @ (posedge ahb_clock or negedge resetn) begin
if (!resetn)
ahb_hrdata <= 0;
else if (rd_en_d3)
ahb_hrdata <= ram_qd;
end

always @ (posedge ahb_clock or negedge resetn) begin
if (!resetn)
ram_qd <= 0;
else if (rd_en_d2)
ram_qd <= ram_q;
end

assign ram_addr = haddr_reg[ADDR_BITS-1:2];
assign ram_data = ahb_hwdata;
assign ram_rden = rd_en_d1;

endmodule