core-clk 120MHZ时候 HSE一定要改为60MHZ 必须 MC_CGM_MUX_0_DIV3 from "1" to "2" 否则外部复位后 因为调试器将延迟时钟初始化，足以让SBAF停放HSE核心。在HSE堆芯停驻之前更改此时钟将导致HSE堆芯锁定，从而触发HSE WDG复位。
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60MHz should be the default HSE_CLK due to HSE Gasket defaults. If you wish to run the HSE at 120MHz you will need to configure the gasket in the DCF Record area. See S32K3xx_DCF_clients.xlsx attached to the reference manual for details.
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You can check the reported reset reason using the ERM - this will indicate either an external reset or indicate the internal reset source
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Please make sure that all cores have entered WFI before calling the clock switch:
This can be a common cause of the described behavior, as the debugger will delay clock initialization enough for the SBAF to park the HSE core. Changing this clock before the HSE core is parked will cause lockup on the HSE core triggering HSE WDG reset.