verilog HDLBits刷题[Finite State Machines]“Fsm3s”---Simple FSM 3 （synchronous reset）
1、题目
See also: State transition logic for this FSM
The following is the state transition table for a Moore state machine with one input, one output, and four states. Implement this state machine. Include a synchronous reset that resets the FSM to state A. (This is the same problem as Fsm3 but with a synchronous reset.)
| State | Next state | Output | |
|---|---|---|---|
| in=0 | in=1 | ||
| A | A | B | 0 |
| B | C | B | 0 |
| C | A | D | 0 |
| D | C | B | 1 |
2、代码
module top_module( input clk, input in, input reset, output out); // reg [3:0] state,next_state; parameter A=0, B=1, C=2, D=3; // State transition logic: Derive an equation for each state flip-flop. assign next_state[A] = state[0]&(~in) | state[2]&(~in); assign next_state[B] = state[0]&(in) | state[1]&(in)|state[3]&(in); assign next_state[C] = state[1]&(~in) | state[3]&(~in); assign next_state[D] =state[2]&(in); always @(posedge clk)begin if(reset) state<=4'd1; else state<=next_state; end // Output logic: assign out = (state[D]==1'b1); endmodule3、结果