verilog HDLBits刷题[Finite State Machines]“Exams/ece241 2014 q5b”---Q5b:Serial two‘s complementer

1、题目

2、分析

独热码，只有1bit为1，其它位全为0

3、代码

module top_module ( input clk, input areset, input x, output z ); parameter A=2'b01,B=2'b10; reg [1:0]state,next_state; always@(posedge clk,posedge areset)begin if(areset) state<=A; else state<=next_state; end always@(*)begin case(state) A:begin next_state=x?B:A;z=x;end B:begin next_state=B;z=~x;end default:begin next_state=A;z=1'b0;end endcase end endmodule

4、结果